The present technology relates to a solid-state image sensor, a control method therefor, and an electronic device, and particularly relates to a solid-state image sensor, a control method therefor, and an electronic device which make it possible to generate an image suitable for use.
In a general image sensor which reads charges accumulated in a light receiving part such as a photo diode through a MOS transistor, a readout operation is executed in units of a pixel, a row, or the like, and thus it is not possible to synchronize, in all of pixels, an exposure time period during which photocharges are accumulated. Accordingly, in such a case that a subject is moving, a captured image has distortion.
Hence, a pixel structure as illustrated in FIG. 1 is known. In the structure, unit pixels 20A each has a memory part (MEM) 23 therein, a charge accumulated in a photo diode (PD) 21 is transferred to the memory part 23 in each pixel simultaneously, and the charge is held until a readout operation to be performed in row unit. This configuration enables an image capturing operation using global exposure employing the same exposure time period for all the pixels for image capturing.
FIG. 2 is a timing chart illustrating an example of driving the unit pixels 20A in an exposure and charge accumulation time period. Firstly, in a time period between time t1 and time t2, a first transfer gate (TRX) 22, a second transfer gate (TRG) 24, and a reset transistor (RST) 26 are turned on to discharge charges in the photo diode 21 and the memory part 23.
Next, in a time period between time t2 and time t3, a charge newly obtained from light from the subject after the charge discharging is accumulated in the photo diode 21 in each pixel simultaneously. Then, in a time period between time t3 and time t4, the second transfer gate 24 and the reset transistor 26, and then the first transfer gate 22 are turned on, so that the charge accumulated in the photo diode 21 is transferred to the memory part 23 in each pixel simultaneously.
FIG. 3 is a timing chart illustrating an example of driving the unit pixels 20A in readout scanning (reading out a signal charge in row units). Firstly, a control pulse SEL and thereafter a control pulse RST are turned on. Then, in a time period between time t11 and time t12, a noise level of a floating diffusion (FD) 25 is read out. Then, a transfer pulse TRG in a time period between time t12 and time t13 is turned on, the second transfer gate 24 transfers a charge held in the memory part 23 to the floating diffusion 25. Then, in a time period between time t13 and time t14, a voltage corresponding to the charge held in the floating diffusion 25 is read out as a signal level. A difference between the signal level read out in this way and the noise level previously read out is obtained, so that a signal level with noise removed is thereby obtained.
Meanwhile, as illustrated in a timing chart in FIG. 4, the exposure and charge accumulation and the readout scanning of two-dimensionally arranged pixels can be performed in the same time period. In other words, as illustrated in FIG. 4, when a control pulse RST is turned on while a control pulse SEL is turned on, the noise level of the floating diffusion 25 is read out in a time period between time t22 and time t23. Moreover, when a transfer pulse TRG is turned on, a voltage corresponding to the charge held in the floating diffusion 25 after being transferred from the memory part 23 is read out as a signal level in a time period between time t24 and time t25. Note that the signal charge is read out in row units in a time period from time t22 to time t25.
Thereafter, the control pulse SEL is turned off, then the control pulse RST, a transfer pulse TRX, and the transfer pulse TRG are turned on, and further the transfer pulse TRX, the transfer pulse TRG, and the control pulse RST are turned off in this order. Thereby, charges in the photo diode 21 and the memory part 23 are discharged in a time period between time t25 and time t26. Note that charges in a plurality of rows are simultaneously discharged in the time period between time t25 and time t26. In the exposure and accumulation after time t26, a charge newly obtained from light from the subject is accumulated in each photo diode 21.
As described above, charge signals are serially read out in row units in the unit pixels 20A. While the readout is performed on a certain row, the charge discharging operation is executed for a plurality of rows or for all the pixels simultaneously. While a pixel signal is readout in the continued row scanning, the exposure and accumulation operation is continued and a charge transfer operation is executed for a plurality of rows or for all the pixels simultaneously.
Meanwhile, in the structure of the pixel illustrated in FIG. 1, the pixel is provided with the memory part 23, and thus has a lower maximum charge amount (saturation charge amount) allowed to be accumulated in the photo diode 21 than a pixel without the memory part 23 has. Since a substantial saturation charge amount is a smaller one of the maximum charge amount allowed to be accumulated in the photo diode 21 and the maximum charge amount allowed to be accumulated in the memory part 23, it is necessary to maximize both the photo diode 21 and the memory part 23. In other words, the saturation charge amount of the pixel including the memory part 23 is approximately half of the saturation charge amount of the pixel without the memory part 23.
FIG. 5 is a cross-sectional diagram illustrating a structure of a unit pixel corresponding to the circuit diagram in FIG. 1. In the structure illustrated in FIG. 5, the area (volume) of the photo diode 21 is smaller than that of the photo diode 21 of the unit pixel without the memory part 23. Further, an increased area of the photo diode 21 leads to a decreased area of the memory part 23, and thus it is not possible to maintain the maximum charge amount of the photo diode 21. Consequently, it is not possible to increase a charge amount allowed to be handled. Specifically, FIG. 6 illustrates how a charge is transferred from the photo diode 21 to the memory part 23 in a time period between time t41 and time t43. It is obvious that an increased area of the photo diode 21 leads to a decreased area of the memory part 23.
Hence, the applicant proposes a structure of a pixel as illustrated in FIG. 7. In the structure, an overflow path 37 is formed between a photo diode 21 and a memory part 23 which are provided in the pixel (see JP 2009-268083A, for example). Employing the structure makes it possible to accumulate charges in both the photo diode 21 and the memory part 23 in the exposure time period and thus to increase the saturation charge amount. In another configuration, a barrier between a photo diode 21 and a memory part 23 is intermittently modulated during the exposure time period, and thereby it is also possible to accumulate charges in both the photo diode 21 and the memory part 23, like the case of forming the overflow path 37.
Note that the applicant proposes a structure of a pixel, as illustrated in FIG. 8, including a charge discharging gate 29 for directly discharging a signal charge in a photo diode 21 without passing through a floating diffusion 25 (see JP 2004-111590A, for example). Employing the structure makes it possible to prevent an unrequired charge from leaking from the photo diode 21 into the floating diffusion 25 while a charge is accumulated in a memory part 23, that is, while a charge signal is serially read out in each row. The applicant also proposes feasibility of an exposure operation in a shorter time than a one-frame readout time period, the operation being achieved in such a manner that a channel electric-potential at the time of turning on a charge discharging gate 29 is set higher than an electric-potential causing the photo diode 21 to be completely depleted (see JP 2008-177593A, for example).
Further, the applicant proposes a structure in which: pixels each include two memory parts having different capacitances per unit area and properties at dark; and overflow paths are formed between a photo diode and one of the memory parts and between the photo diode and the other (see JP 2011-199816A, for example). When the structure is employed, it is possible to efficiently increase a saturation charge amount by selectively using one of the two memory parts according to a signal charge amount.